Effects of age on amplitude-modulated cVEMP temporal modulation transfer function

With the aging population on the rise, the need for effective assessment tools to identify risk factors for falls among the elderly is paramount. One independent risk factor for falls is vestibular impairment, but the available vestibular diagnostic tests have limitations. A promising new methodology: amplitude-modulated tones to elicit a vestibular-evoked myogenic potential (AMcVEMP), offers a more detailed examination of vestibular (sacculo-collic reflex) functions. This method assesses non-linearities, synchrony, and magnitude, providing a more thorough evaluation compared to the conventional transient cVEMP. So far, AMcVEMP has only been utilized in young adults. The current study aimed to investigate the impact of age on the AMcVEMP temporal modulation transfer function (TMTF), determine the shape and limit of the AMcVEMP TMTF, and assess non-linearity across a range of modulation frequencies. The study included 49 healthy participants, categorized into three age groups. AMcVEMP responses were elicited using a carrier-frequency of 500 Hz and 10 modulation frequencies. An FFT-based approach was employed to analyze the responses, focusing on amplitude, signal-to-noise ratio (SNR), phase coherence (PC), and non-linearity. To measure non-linearity, harmonics of the modulation frequencies were analyzed. The AMcVEMP responses exhibited characteristics consistent with saccular rectification. The AMcVEMP amplitude, SNR, and PC reduced with increasing age. The effects of age were less pronounced for PC, showing 100% response rates among older adults. Further, AMcVEMP TMTF range reduced with age for all measures. The shape of the AMcVEMP TMTF resembled bandpass filter among young adults and got narrower with age. Lastly, for the non-linearity measures, harmonics were robust in most young, some middle-aged and fewer older adults, indicating loss of non-linearity with aging. AMcVEMP offers several advantages in assessing older adults compared to conventional cVEMP: higher response rates and the ability to examine and quantify the magnitude, synchrony, and non-linearity from the sacculo-collic reflex. This study advances our overall understanding of age-related changes in the vestibular system. Further utility of AMcVEMP in clinical populations will advance our comprehension of vestibular pathophysiology. Furthermore, linking vestibular non-linearity with functional balance may facilitate the development of strategies to mitigate the risk of falls among older adults

Robustness of Power Analysis Attack Resilient Adiabatic Logic: WCS-QuAL under PVT Variations

In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of % Normalized Energy Deviation (NED) and % Normalized Standard Deviation (NSD) at all simulated frequencies. Also, all 2-input gates using WCS-QuAL dissipate nearly equal energy for all possible input transitions. In addition, the energy dissipated by WCS-QuAL approaches to the energy dissipation of EESPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance, GF (24) bit-parallel multiplier was implemented as a design example. The impact of Process-Voltage-Temperature (PVT) variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT variations and when the power supply is scaled down compared to EE-SPFAL and SPGAL. At lower technology, WCS-QuAL, shows more improvement in energy dissipation than EE-SPFAL

Energy efficiency of 2- Step power-clocks for adiabatic logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient `rule-of-thumb' in practical designs

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In this paper, we shall present a novel PAA resilient adiabatic logic which has a symmetric structure and exhibits the least variations in current peaks for basic gates as well as in 8-bit Montgomery multiplier. The proposed logic has been compared with two recently proposed secure adiabatic logic designs for operating frequencies ranging from 1MHz to 100MHz and power-supply scaling ranging from 0.6V to 1.8V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) under the said frequency variations. All the 2-input gates that deploy the proposed logic dissipate nearly the same average energy within 0.2% of each other at all the frequencies simulated and thus, along with the dataindependence,gate-function-independence is achieved. The paper will also report on the energy dissipated by the proposed logic which approaches that of the existing logic designs as the output load capacitance is increased above 100fF. The simulation results of the 8-bit adiabatic Montgomery multiplier show that the proposed logic exhibits the least value of NED and NSD under the said frequency variations and power-supply scaling. Finally, the paper will report on the current waveform graphs for variations in current peaks under power-clock scaling

Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits

A Novel Power Analysis Attack Resilient Adiabatic Logic without Charge Sharing

In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn’t require any charge sharing between the output nodes of the gates. The proposed logic also removes the non-adiabatic losses (NAL) during the evaluation phase of the power-clock. We investigate and compare our proposed and the existing secure adiabatic logic across a range of “power-clock” frequencies on the basis of percentage Normalized Energy Deviation (%NED), percentage Normalized Standard Deviation(%NSD) and average energy dissipation. The pre-layout and post-layout simulation results show that our proposed logic exhibits the least value of %NED and %NSD in comparison to the existing secure adiabatic logic designs at the frequency ranging from 1MHz to 100MHz. Also, our proposed logic consumes the lowest energy

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations

Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present “Without Charge-Sharing Quasi-Adiabatic Logic”, WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz

Adiabatic Circuits for Power-Constrained Cryptographic Computations

This thesis tackles the need for ultra-low power operation in power-constrained cryptographic computations. An example of such an application could be smartcards. One of the techniques which has proven to have the potential of rendering ultra-low power operation is ‘Adiabatic Logic Technique’. However, the adiabatic circuits has associated challenges due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors is considered for the power-clock generation and several design rules and trade-offs between the circuit complexity and energy efficiency of the PCG using n-step charging circuits have been proposed. Since pipelining is inherent in adiabatic logic design, careful selection of architecture is essential, as otherwise overhead in terms of area and energy due to synchronization buffers is induced specifically, in the case of adiabatic designs using 4-phase power-clocking scheme. Several architectures for the Montgomery multiplier using adiabatic logic technique are implemented and compared. An architecture which constitutes an appropriate trade-off between energy efficiency and throughput is proposed along with its methodology. Also, a strategy to reduce the overhead due to synchronization buffers is proposed. A modification in the Montgomery multiplication algorithm is proposed. Furthermore, a problem due to the application of power-clock gating in cascade stages of adiabatic logic is identified. The problem degrades the energy savings that would otherwise be obtained by the application of power-clock gating. A solution to this problem is proposed. Cryptographic implementations also present an obvious target for Power Analysis Attacks (PAA). There are several existing secure adiabatic logic designs which are proposed as a countermeasure against PAA. Shortcomings of the existing logic designs are identified, and two novel secure adiabatic logic designs are proposed as the countermeasures against PAA and improvement over the existing logic designs

Identifying Heavy-Flavor Jets Using Vectors of Locally Aggregated Descriptors

Jets of collimated particles serve a multitude of purposes in high energy collisions. Recently, studies of jet interaction with the quark-gluon plasma (QGP) created in high energy heavy ion collisions are of growing interest, particularly towards understanding partonic energy loss in the QGP medium and its related modifications of the jet shower and fragmentation. Since the QGP is a colored medium, the extent of jet quenching and consequently, the transport properties of the medium are expected to be sensitive to fundamental properties of the jets such as the flavor of the parton that initiates the jet. Identifying the jet flavor enables an extraction of the mass dependence in jet-QGP interactions. We present a novel approach to tagging heavy-flavor jets at collider experiments utilizing the information contained within jet constituents via the \texttt{JetVLAD} model architecture. We show the performance of this model in proton-proton collisions at center of mass energy $\sqrt{s} = 200$ GeV as characterized by common metrics and showcase its ability to extract high purity heavy-flavor jet sample at various jet momenta and realistic production cross-sections including a brief discussion on the impact of out-of-time pile-up. Such studies open new opportunities for future high purity heavy-flavor measurements at jet energies accessible at current and future collider experiments.Comment: 18 pages, 6 figures and 3 tables. Accepted by JINS

Journal Self-Citation VIII: An IS Researcher in the Dual Worlds of Author-Reader and Author-Institution

This paper responds to the question of whether it is ethical for a journal editor to request an author to cite papers from a journal to which one is submitting an article. To craft a response to this question, two sets of relationships are explored. The first set is an author-reader relationship, and the second set is an author-institution or community relationship. In these dual relationships, the author is considered to be an IS researcher who publishes and disseminates knowledge through the channel of research journals. The reason for articulating these twofold relationships is to go beyond the common belief that the author is the sole and autonomous source of knowledge creation and distribution. We posit that: (1) an author cannot exist isolated from the reader, and (2) an author exists only as a part of an institutional system which opens and at the same time constrains an author’s knowledge production. In other words, an author is destined to create knowledge within the constrained system. For that very reason, it is important to understand the author as a function of conditional discourse of a specific institution. We conclude that editors’ requests for an author to cite papers from a journal to which one is submitting an article is ethically critical to: (1) build a good author-reader relationship, and (2) produce rich and plural knowledge which is “good” for advancing learning in the global community